Logic Analyzer IP Core

A systemverilog implementation of the data structures: priority queue, queue and stack

An FPGA implementation of Cummings' Asynchronous FIFO

Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA

Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

7-segment snake using a microcontroller

UART Receiver and Transmitter using Terasic DE-10 Standard FPGA

This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.

Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA

Basic Stopwatch Design using Terasic DE-10 Standard FPGA

This implements a simple median filter on hardware.

A Tic-Tac-Toe with multiple level levels and flashing lights implementation using Hardware Definition Language (Verilog) and DE10-Lite Altera Max 10 FPGA.